High-capacity, high-density flash memory such as BiCS FLASH (3D NAND) is prone to bit inversion due to minute charge loss (retention degradation) and interference between adjacent cells (read disturb), making robust error correction (ECC: Error Correction Code) essential. While this is usually handled by hardware (LDPC or BCH engine), we have created sample code here that simulates a process where the device driver (software layer) controls and monitors the hardware ECC engine, and performs read...